Views: 0 Author: Site Editor Publish Time: 2026-05-19 Origin: Site
Space-Solar Cell in Thin Ge Wafers
Cracking in thin Ge wafers used for multijunction solar cells (MJSCs) arises from a combination of thermal stress from CTE mismatch, surface/edge defects that act as crack initiation sites, and mechanical damage during thinning, dicing, and bonding. The solution requires a multi-pronged approach addressing substrate preparation, processing parameters, and packaging design.

1. Problem Definition & Requirements
Material System: Monocrystalline Ge wafer (substrate) + III-V compound semiconductor stack (InGaP / InGaAs / Ge or similar) deposited by MOVPE, plus a cover glass (fused silica or borosilicate) bonded via adhesive.
Key Constraints:
• Ge is brittle (fracture toughness ~0.6 MPa·m⁰·⁵) and has a CTE of ~5.9 × 10⁻⁶ /°C, versus fused silica at ~0.55 × 10⁻⁶ /°C — a ~10× mismatch
• Space solar cells cycle between −170 °C and +140 °C in orbit, generating repeated thermomechanical fatigue
• Wafer thinning (to reduce mass for space applications) reduces flexural rigidity, amplifying bending stress
Success Criteria: Zero wafer fracture during MOVPE growth, post-growth thinning, dicing, bonding, and in-service thermal cycling; surface roughness Ra ≤ 17 nm on the backside; edge roughness minimized to reduce crack nucleation sites.

2. Root Cause Analysis
3. Solution Space & Approaches
Boeing's patented approach specifically combines S1 + S2 + S3 to address CTE mismatch between fused silica cover glass and the Ge-backed MJSC, achieving backside Ra reduction from ≥50 nm to ≤17 nm and Ge thickness >200 µm.
EP3719856A1 The Cactus Materials low-stress passivation approach uses low-stress dielectric layers to reduce thermomechanical stress in back-contact multijunction cells thinned to <150 µm.
The Applied Materials approach (S4) reduces the epitaxial deposition rate to <1 µm/min until the layer reaches 2–30 µm thickness to inhibit slip and microcracking during semiconductor wafer epitaxy, and removes bridge materials between wafer and support before cooling to prevent thermally-induced stress.
Shin-Etsu Handotai's peripheral terrace/trench processing (S6) prevents cracks generated at the chamfered outer edge from extending toward the wafer center during epitaxial growth.
4. Solution Comparison
5. Scientific & Technical Basis
6. Implementation Strategy
Recommended integrated process sequence:
• Substrate qualification — Receive Ge wafers with specified dislocation density and surface roughness; apply peripheral terrace/trench processing to chamfered edges before loading into MOVPE reactor.
• MOVPE growth — Use controlled slow ramp rates during heat-up and cool-down; initiate III-V deposition at <1 µm/min until the first epilayer reaches 2–30 µm; remove any wafer-susceptor bridge material before cooling.
Target MOVPE growth conditions that minimize reactor-ceiling atom re-deposition into epilayers.
• Post-growth backside thinning — Perform coarse + fine mechanical grinding on the backside (second side), targeting final Ge thickness >150 µm (ideally >200 µm for space applications).
EP3719856A1 Follow immediately with wet chemical etch to remove grinding-induced crystal defects and reduce Ra to ≤17 nm.
CA3075149C Use low-temperature lapping conditions to minimize subsurface damage depth.
• Dicing — Use a diamond-coated saw rather than scribe-and-break to produce smooth, low-defect edges that minimize crack initiation sites.
• Cover glass bonding — Bond fused silica cover glass using a flexible silicone-based adhesive (e.g., space-grade encapsulant); cure at <100 °C to minimize frozen-in thermal stress from the cure temperature offset.
• Qualification testing — Thermal cycle between −170 °C and +140 °C; inspect edges and backside by optical microscopy and SEM; measure wafer bow before and after each process step.
7. Risks, Constraints & Mitigation
8. Recommendations
Primary recommendation: Implement the combined S1 + S2 + S3 process bundle — backside grind-and-etch to >150 µm (preferably >200 µm) with Ra ≤17 nm, diamond-saw dicing, and low-temperature (<100 °C) silicone adhesive cure. This is the most directly validated approach for Ge-backed MJSCs in space environments, targeting CTE mismatch failure.
Secondary recommendation: Add S4 (controlled MOVPE ramp rates and slow initial deposition) as an in-reactor measure that costs minimal throughput but significantly reduces thermally-driven microcracking during growth.
For ultra-thin wafers (<150 µm): Add S6 (peripheral trench processing) and low-stress passivation layers (S variant of S3) to compensate for the reduced mechanical rigidity.
Fallback: If diamond-saw dicing is not available, edge-polish the die after scribe-and-break to remove the most severe crack initiation sites before cover-glass bonding.
The key insight across all solutions is that Ge's intrinsically low fracture toughness means crack initiation must be suppressed at every stage — surface, edge, and bulk — because once a defect of sufficient size exists, the CTE-mismatch-driven stress in the space thermal environment will propagate it to failure. No single intervention is sufficient; the combination of defect minimization at the backside, edges, and epilayer interface, together with stress reduction at the bonding stage, provides robust crack prevention.
